The present invention relates generally to the semiconductor integrated circuit (IC) chip design and fabrication, and more particularly to identifying and locating IC failures without using any layout versus schematic (LVS) verification tool.
New IC creation is an extremely time-consuming, labor-intensive, and costly endeavor. The IC creation process can be divided into the IC design/verification stage and the IC fabrication/test stage. Previously, many integrated device manufacturers (IDMs) designed and manufactured their new ICs within their own company plants and fabrication facilities (fabs). However, as the cost of building and operating the fabs have spiraled upward, many of these IDMs have eliminated their own fabs and utilized “pure play” foundries to fabricate their IC designs. These companies are now known as fabless IC companies. Foundries run multiple fabless companies IC designs in their fabs using their own internally developed fabrication processes.
There are several advantages with respect to the fabless business model. For example, the startup of a fabless IC company requires only a relatively modest investment in computer aided design (CAD) systems. The cost of a typical state-of-the-art fab now exceeds $2 billion. The fabless IC company reaps the benefits of manufacturing economies of scale. The fabless IC company can focus its efforts on its area of the greatest expertise, product definition, design, and development.
Although the fabless business model has many advantages, there are pitfalls as well. For example, the design handoff information from the fabless IC company or IDM to the circuit manufacturer is very complex. All pertinent fabrication, test, and troubleshoot information need to be available to the circuit manufacturer to quickly resolve technical issues to minimize the turnaround time. Although this is desirable, in reality, the fabless IC company only supplies the minimum necessary data to the circuit manufacturer to protect its proprietary design information.
Also, the fabless company or IDM typically utilizes a “Layout versus Schematic” (LVS) tool for verification of the entire IC design prior to its handoff to the circuit manufacturer for fabrication. The LVS testing is an essential step in IC design and validates the consistency between the logical view (schematic or netlist) versus the physical view (layout or masking polygon). Various LVS tool suites are available to the fabless IC companies from CAD vendors. The fabless IC company or IDM can therefore run their selected LVS tools. The resultant database created from the LVS verification step is then utilized by the fabless IC company and IDM to associate the logical netlist information to the physical layout database of the IC.
Today's deep sub-micron geometries ICs, such as the system on a chip (SOC) designs, contain more than a million gates as well as multiple functional blocks (SRAM, PLL, analog converters, etc). As such, the LVS verification on today's ICs requires tremendous computing resources, extensive test time, and technical resources to perform the verification.
For the circuit manufacturer, these LVS results may not be accessible due to the proprietary information the LVS results contain. Only limited mask tooling information (physical view) is available to the circuit manufacturer. Also, the complete netlist information created for the IC design also may not be available to the circuit manufacturer due to its proprietary nature.
Therefore, desirable in the art of IC fabrication for a circuit manufacturer are alternative methods to identify and locate IC failures after IC fabrication without using any LVS verification tool information for minimizing the IC fabrication turnaround time.